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73S8009R Low Cost Versatile Smart Card Interface
Simplifying System IntegrationTM DS_8009R_056 APPLICATIONS * DESCRIPTION The 73S8009R is a very low-cost level shifter, single smart card (ICC) interface IC. The device includes a level shifter interface between a 3.3 V (typical) logic circuitry (host microcontroller) and an ISO-7816 / EMV smart card. The 73S8009R is designed to provide full electrical compliance with ISO-7816-3 EMV4.1 (EMV2000) and GSM11-11 specifications. In normal operating mode, for maximum designer flexibility, the host microcontroller is responsible for card activation and deactivation. The 73S8009R incorporates an ISO-7816-3 deactivation sequencer that controls the card signals in case of fault detection and card removal. Card presence and faults are reported to the host through an interrupt output. When the 73S8009R is ready to support a card with the selected voltage, a RDY signal informs the host it can initiate the card activation sequence. The 73S8009R supports 5V, 3V and 1.8V cards. Selection is done through 2 dedicated digital inputs. Level-shifters drive the card signals with the selected card voltage coming from an internal Low Drop-Out (LDO) voltage regulator. The LDO regulator is powered by a dedicated power supply input, VPC. Digital circuitry is separately powered by a digital power supply, VDD. Emergency card deactivation is initiated upon card extraction or any fault generated by the protection circuitry. The fault can be a card over-current, a VDD (digital power), a VPC (regulator power), a VCC (card power output) or an over-heating fault. A chip select digital input drives internal latches that allow the host controller to control multiple 73S8009R ICs in parallel. A power down digital input also allows the host microcontroller to place the IC in a very low-power mode making the 73S8009R particularly suitable for low-power and battery-powered applications. Auxiliary I/O lines are also available (SO28 package only) and make the 73S8009R suitable for all kind of cards, including synchronous (memory) cards. Rev. 1.3 * * * Set-Top-Box Conditional Access and Pay-per-View
SIM card readers in DECT and GSM phones, GPRS, WIFI and VOIP devices
DATA SHEET
October 2009
Point of Sales & Transaction Terminals General purpose smart card readers
ADVANTAGES * Lowest cost smart card interface IC on the market Ideal to replace discrete designs in POS terminals and Set-Top-Boxes Traditional step-up converter is replaced by an LDO regulator Greatly reduced power dissipation Fewer external components are required Better noise performance Very low power dissipation Small format (4x4x0.8 mm) QFN20 package option
*
*
FEATURES * Card Interface: * Complies with ISO-7816-3, EMV 4.0 and GSM 11-11 specifications * An LDO voltage regulator provides 1.8V / 3V / 5V to the card from an external power supply input * Provides at least 90 mA to the card * ISO-7816-3 card emergency deactivation sequencer * Protection includes 3 voltage supervisors that detect voltage drops on VCC (card), VDD (digital) and VPC (regulator) power supplies * Over-current detection, 150 mA max. * 2 card detection inputs, 1 for each user polarity * Auxiliary I/O lines for C4 / C8 contact signals * Card CLK clock frequency up to 20 MHz
(c) 2009 Teridian Semiconductor Corporation
1
73S8009R Data Sheet * System Controller Interface * Five signal images of the card signals (RSTIN, CLKIN, IOUC, AUX1UC, AUX2UC) * Two inputs select card voltage (CMDVCC%, CMDVCC#) * Two Interrupt outputs (OFF, RDY) inform the system controller of card presence / faults and the interface status * Chip select input (CS) * Power down input (PWRDN) *
DS_8009R_056 Regulator Power Supply (VPC): * Class A-B-C readers: 5V, 3V and 1.8V cards: 4.75 V to 6.0 V Digital Interface (VDD): 2.7 V to 3.6 V 6 kV ESD protection on the card interface SO28 or QFN20 package
* * *
FUNCTIONAL DIAGRAM
VDD [17] 28
VPC [9] 15
VCC FAULT
VOLTAGE REFERENCE
bias currents
VPC FAULT vref
LDO REGULATOR
20 [12] 22 [14] VCC GND
CMDVCC5 CMDVCC3
8 [2] 9 [3] 4 [20]
OFF RDY PWRDN CS 10 [4] RSTIN 11 [5] CLKIN 12 [6] 13 [7] 1 [18]
CONTROL LOGIC
RESET BUFFER
21 [13] RST
CLOCK BUFFER
19 [11] CLK 26 [16] 16 [10] PRES PRES
1.5MHz
TEMP FAULT
R-C OSC.
5 [1] IOUC AUX1UC AUX2UC 6 7
OVER TEMP
25 [15]
I/O AUX1 AUX2
SMART CARD I/O BUFFERS
24 23
27 GND
Pin numbers reference the SO28 package [Pin numbers] reference the QFN20 Package
Figure 1: 73S8009R Block Diagram
Rev. 1.3
2
DS_8009R_056
73S8009R Data Sheet
Table of Contents
1 2 Pinout ............................................................................................................................................. 5 Electrical Specifications................................................................................................................ 8 2.1 Absolute Maximum Ratings ..................................................................................................... 8 2.2 Recommended Operating Conditions ...................................................................................... 8 2.3 Smart Card Interface Requirements ........................................................................................ 9 2.4 Digital Signals Characteristics ............................................................................................... 11 2.5 DC Characteristics ................................................................................................................ 11 2.6 Voltage / Temperature Fault Detection Circuits...................................................................... 12 Applications Information ............................................................................................................. 13 3.1 Example 73S8009R Schematics ........................................................................................... 13 3.2 System Controller Interface ................................................................................................... 14 3.3 Power Supply and Voltage Supervision ................................................................................. 14 3.4 Card Power Supply ............................................................................................................... 14 3.5 Over-temperature Monitor ..................................................................................................... 15 3.6 Activation and Deactivation Sequence................................................................................... 15 3.7 OFF and Fault Detection ....................................................................................................... 16 3.8 Power-down Operation.......................................................................................................... 17 3.9 Chip Select ........................................................................................................................... 18 3.10 I/O Circuitry and Timing......................................................................................................... 18 Mechanical Drawings .................................................................................................................. 20 4.1 20-pin QFN ........................................................................................................................... 20 4.2 28-Pin SO ............................................................................................................................. 21 Ordering Information ................................................................................................................... 22 Related Documentation ............................................................................................................... 22 Contact Information..................................................................................................................... 22
3
4
5 6 7
Revision History .................................................................................................................................. 23
Rev. 1.3
3
73S8009R Data Sheet
DS_8009R_056
Figures
Figure 1: 73S8009R Block Diagram ......................................................................................................... 2 Figure 2: 73S8009R 20-Pin QFN Pinout .................................................................................................. 5 Figure 3: 73S8009R 28-Pin SO Pinout..................................................................................................... 5 Figure 4: Typical 73S8009R Application Schematic ............................................................................... 13 Figure 5: Activation Sequence ............................................................................................................... 15 Figure 6: Deactivation Sequence ........................................................................................................... 16 Figure 7: OFF Activity Outside and Inside a Card Session ..................................................................... 17 Figure 8: Power-down Operation ........................................................................................................... 17 Figure 9: CS Timing Definitions.............................................................................................................. 18 Figure 10: I/O and I/OUC State Diagram ................................................................................................ 19 Figure 11: I/O to I/OUC Delay Timing Diagram....................................................................................... 19 Figure 12: 20-pin QFN Package Dimensions ......................................................................................... 20 Figure 13: 28-Pin SO Package Dimensions ........................................................................................... 21
Tables
Table 1: 73S8009R Pin Definitions .......................................................................................................... 6 Table 2: Absolute Maximum Device Ratings ............................................................................................ 8 Table 3: Recommended Operating Conditions ......................................................................................... 8 Table 4: DC Smart Card Interface Requirements ..................................................................................... 9 Table 5: Digital Signals Characteristics .................................................................................................. 11 Table 6: DC Characteristics ................................................................................................................... 11 Table 7: Voltage / Temperature Fault Detection Circuits......................................................................... 12 Table 8: Choice of VCC Pin Capacitor ................................................................................................... 15 Table 9: Order Numbers and Packaging Marks ...................................................................................... 22
4
Rev. 1.3
DS_8009R_056
73S8009R Data Sheet
1 Pinout
The 73S8009R is supplied as a 20-pin QFN package and as a 28-pin SO package.
TEST1 PRES 16
15 14
OFF
20
19
18
CS
I/OUC CMDVCC% CMDVCC# RSTIN CLKIN
1 2 3 4 5
17
VDD
I/O VCC RST GND CLK
TERIDIAN 73S8009R
13 12 11
PWRDN
TEST2
RDY
VPC
Figure 2: 73S8009R 20-Pin QFN Pinout
(Top View)
CS TEST1 N/C OFF I/OUC AUX1UC AUX2UC CMDVCC% CMDVCC# RSTIN CLKIN RDY PWRDN TEST2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
PRES
VDD GND PRES I/O AUX1 AUX2 VCC RST GND CLK N/C N/C PRES VPC
Figure 3: 73S8009R 28-Pin SO Pinout
Rev. 1.3
10
6
7
8
9
5
73S8009R Data Sheet Table 1 describes the pin functions for the device. Table 1: 73S8009R Pin Definitions Pin Name I/O AUX1 AUX2 RST CLK Pin (SO28) 25 24 23 21 19 Pin (QFN20) 15 NA NA 13 11 Type Description
DS_8009R_056
Card Interface IO IO IO O O Card I/O: Data signal to/from card. Includes a pull-up resistor to VCC. AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. Card reset: provides reset signal to card. Card clock: provides clock signal to card. The rate of this clock is determined by the external clock frequency provided on pin CLKIN. Card Presence switch: active high indicates card is present. Should be tied to GND when not used, but includes a highimpedance pull-down current source. Card Presence switch: active low indicates card is present. Should be tied to VDD when not used, but includes a highimpedance pull-up current source. Card power supply - logically controlled by the sequencer, output of LDO regulator. Requires an external filter capacitor to GND. Card ground. Clock source for the card clock. This pin must be tied to GND in typical applications. This pin must be tied to GND in typical applications. Non-connected pin. System interface supply voltage and supply voltage for internal circuitry. LDO regulator power supply source. GND I Ground. When CS = 1, the control and signal pins are configured normally. When CS is set low, CMDVCC%, RSTIN, and CMDVCC# are latched, IOUC, AUX1UC, and AUX2UC are set to high-impedance pull-up mode and do not pass data to or from the smart card. Signals RDY and OFF are disabled to prevent a low output and the internal pull-up resistors are disconnected. Interrupt signal to the processor. Active low, multi-function indicating fault conditions and card presence. Open drain output configuration. It includes an internal 20 k pull-up to VDD. The pull-up is disabled in PWRDN and CS=0 modes. Rev. 1.3
PRES
26
16
I
PRES
16
10
I
VCC
22
14
PSO
GND CLKIN TEST1 TEST2 NC VDD VPC GND CS
20 11 2 14 3,17,18 28 15 27 1
NA 5 19 8 NA 17 9 12 18
GND I - - -
Miscellaneous Inputs and Outputs
Power Supply and Ground
Microcontroller Interface
OFF
4
20
O
6
DS_8009R_056 Pin Name I/OUC AUX1UC AUX2UC CMDVCC% CMDVCC# Pin (SO28) 5 6 7 8 9 Pin (QFN20) 1 NA NA 2 3
73S8009R Data Sheet
Type I/O I/O I/O I I
Description System controller data I/O to/from the card. Includes a pullup resistor to VDD. System controller auxiliary data I/O to/from the card. Includes a pull-up resistor to VDD. System controller auxiliary data I/O to/from the card. Includes a pull-up resistor to VDD. Logic low on one or both of these pins will cause the LDO to ramp the Vcc supply to the smart card and smart card interface to the value described in the following table: CMDVCC% CMDVCC# VCC Output Voltage 0 0 1.8 V 0 1 5.0 V 1 0 3.0 V 1 1 LDO off Refer to for additional information on the CMDVCC% and CMDVCC# operation.
RSTIN RDY
10 12
4 6
I O
Reset Input. This signal is the reset command to the card. Signal to controller indicating the 73S8009R is ready because VCC is above the required value after CMDVCC% and/or CMDVCC# is asserted low. A 20 K pull-up resistor to VDD is provided internally. The pull-up is disabled in PWRDN and CS=0 modes. PWRDN=1 puts the circuit into low-power mode with all analog functions disabled. The circuit will recover from the PWRDN state in the same manner as recovery from a POR event, taking approximately 1 ms. PWRDN assertion when either CMDVCC% or CMDVCC# is low has no effect and is ignored. There is no pull-up or pull-down provided on this pin.
PWRDN
13
7
I
Rev. 1.3
7
73S8009R Data Sheet
DS_8009R_056
2 Electrical Specifications
This section provides the following: Absolute Maximum Ratings Recommended Operating Conditions Smart Card Interface Requirements Digital Signals Characteristics DC Characteristics Voltage / Temperature Fault Detection Circuits
2.1
Absolute Maximum Ratings
Table 2 lists the maximum operating conditions for the 73S8009R. Permanent device damage may occur if absolute maximum ratings are exceeded. Exposure to the extremes of the absolute maximum rating for extended periods may affect device reliability. Table 2: Absolute Maximum Device Ratings Parameter Supply voltage VDD Supply voltage VPC Input voltage for digital inputs Storage temperature Pin voltage (except card interface) Pin voltage (card interface) ESD tolerance - Card interface pins ESD tolerance - Other pins Rating -0.5 to 4.0 VDC -0.5 to 6.5 VDC -0.3 to (VDD +0.5) VDC -60 C to +150 C -0.3 to (VDD + 0.5) VDC -0.3 to (VCC + 0.5) VDC +/- 6 kV +/- 2 kV
Note: ESD testing on smart card pins is HBM condition, 3 pulses, each polarity referenced to ground. Smart card pins are protected against shorts between any combination of smart card pins.
2.2
Recommended Operating Conditions
Function operation should be restricted to the recommended operating conditions specified in Table 3. Table 3: Recommended Operating Conditions Parameter Supply voltage VDD Supply voltage VPC for Class A-B-C Reader Ambient operating temperature 2.7 to 3.6 VDC 4.75 to 6.0 VDC -40 C to +85 C Rating
8
Rev. 1.3
DS_8009R_056
73S8009R Data Sheet
2.3
Smart Card Interface Requirements
Table 4: DC Smart Card Interface Requirements
Table 4 lists the 73S8009R Smart Card interface requirements.
Symbol
Parameter
Condition
Min
Nom
Max
Unit
Card Power Supply (VCC) Regulator General Conditions: -40 C < T < 85 C, 4.75 V < VPC < 6.0 V, 2.7 V < VDD < 6.0 V VCC Card supply voltage including ripple and noise Inactive mode Inactive mode ICC = 1 mA Active mode; ICC < 65 mA; 5 V Active mode; ICC < 65mA; 5 V, NDS condition Active mode; ICC < 65 mA; 3 V Active mode; ICC < 40 mA; 1.8 V Active mode; single pulse of 100 mA for 2 s; 5 V, fixed load = 25 mA Active mode; single pulse of 100 mA for 2 s; 3 V, fixed load = 25 mA Active mode; current pulses of 40 nAs with peak |ICC | < 200 mA, t < 400 ns; 5 V Active mode; current pulses of 40 nAs with peak |ICC | < 200 mA, t <400 ns; 3 V Active mode; current pulses of 20 nAs with peak |ICC | < 100 mA, t <400 ns; 1.8 V fRIPPLE = 20 kHz - 200 MHz Static load current, VCC > 1.65 V Static load current, VCC > 4.6 V or 2.7 V as selected Class A, B (5 V and 3 V) Class C (1.8 V) CF = 1.0 F CF = 1.0 F on VCC 5 V operation 3 V operation 1.8 V operation -0.1 -0.1 4.65 4.75 2.85 1.68 4.6 - - - - - - - 0.1 0.4 5.25 5.25 3.15 1.92 5.25 V
2.7
-
3.15
4.6
-
5.25
2.7
-
3.15
1.62
-
1.92
ICCrip ICCmax
VCC Ripple Card supply output current
- - - 100 60 0.06 0.075 4.6 2.75 1.65
- - - - - 0.15 0.15 - - - 1.0 3.3
350 40 90 180 130 0.25 0.6 - - -
mV mA
ICCF VSR VSF VRDY
ICC fault current Vcc slew rate, rise rate on activate Vcc slew rate, fall rate on de-activate VCC ready voltage, VCC rising (RDY = 1)
mA V/s V/s V
CF
ISO 7816-13 application External filter capacitor (VCC to GND) EMV 4.1 application CF should be ceramic with low ESR (< 100 m)
F
Rev. 1.3
9
73S8009R Data Sheet Symbol Parameter Condition Min Nom
DS_8009R_056 Max Unit
Interface Requirements - Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC. ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, AUX2UC. VOH VOH VOL VOL VIH VIH VIL VIL VINACT ILEAK IIL IIL ISHORTL ISHORTH t R, t F Output level, high (I/O, AUX1, AUX2) Output level, high (I/OUC, AUX1UC, AUX2UC) Output level, low (I/O, AUX1, AUX2) IOH = 0 A IOH = -40 A IOH = 0 A IOH = -40 A IOL = 1 mA 0.9 * VCC 0.75 * VCC 0.9 * VDD 0.75 * VDD - - - - - - IOL = 0 IOL = 1 mA VIH = VCC VIL = 0 0.6 * VCC 1.8 -0.15 -0.3 - - - - - - - - - - - - - - - - - - - - - - - - - - VCC+0.1 VCC+0.1 VDD+0.1 VDD+0.1 0.15 * VCC 0.3 VCC+0.30 VDD+0.30 0.2 * VCC 0.8 0.1 0.3 10 0.65 0.7 15 15 100 A mA mA mA mA ns V V V V V V V V V
Output level, low (I/OUC, IOL = 1 mA AUX1UC, AUX2UC) Input level, high (I/O, AUX1, AUX2) Input level, high (I/OUC, AUX1UC, AUX2UC) Input level, low (I/O, AUX1, AUX2) Input level, low (I/OUC, AUX1UC, AUX2UC) Output voltage when outside of session Input leakage Input current, low (I/O, AUX1, AUX2)
Input current, low (I/OUC, VIL = 0 AUX1UC, AUX2UC) Short circuit output current Short circuit output current For output low, shorted to VCC through 33 For output high, shorted to ground through 33
Output rise time, fall time For I/O, AUX1, AUX2, CL = 80 pF, 10% to 90%. For I/OUC, AUX1UC, AUX2UC, CL=50 pF, 10% to 90%. Input rise, fall times Internal pull-up resistor Maximum data rate Delay, I/O to I/OUC, AUX1 Edge from master to slave to AUX1UC, AUX2 to measured at 50% point AUX2UC, I/OUC to I/O, AUX1UC to AUX1, AUX2UC to AUX2 (respectively falling edge to falling edge and rising edge to rising edge) Input capacitance Output stable for >200 ns
tIR, tIF RPU FDMAX TFDIO TRDIO
- 8 - 60 -
- 11 - 100 25
1 14 1 200 90
s k
MHz
ns
CIN 10
-
-
10
pF Rev. 1.3
DS_8009R_056 Symbol VOH VOL VINACT IRST_LIM ICLK_LIM Parameter Output level, high Output level, low Output voltage when outside of session Output current limit, RST Output current limit, CLK VCC = 3 V VCC = 5 V CL = 35 pF for CLK, 10% to 90% CL = 200 pF for RST, 10% to 90% Condition IOH = -200 A IOL = 200 A IOL = 0 IOL = 1 mA - - Min 0.9 * VCC 0 - - - - 0.3 0.5 - - 45
73S8009R Data Sheet Nom - - - - - - - - - - - Max VCC 0.15*VCC 0.1 0.3 30 70 - - 8 100 55 % Unit V V V V mA mA V/ns V/ns ns
Reset and Clock for card interface, RST, CLK
CLKSR3V CLK slew rate CLKSR5V CLK slew rate t R, t F Output rise time, fall time
Duty cycle for CLK
CL =35 pF, FCLK 20 MHz
2.4
Digital Signals Characteristics
Table 5: Digital Signals Characteristics
Table 5 lists the 73S8009R digital signals characteristics.
Symbol VIL VIH VOL VOH ROUT |I IL1 |
Parameter Input low voltage Input high voltage Output low voltage Output high voltage Pull-up resistor; OFF, RDY Input leakage current
Condition - - IOL = 2 mA IOH = -1 mA - GND < VIN < VDD
Min -0.3 1.8 - VDD-0.45 -
Nom - - - - 20 -
Max 0.8 VDD+0.3 0.45 - - 5
Unit V V V V k A
Digital I/O except for OSC I/O
2.5
DC Characteristics
Table 6 lists the DC characteristics. Table 6: DC Characteristics Symbol IDD IPC Parameter Supply current Supply current Condition Normal operation Power down VCC on, ICC = 0 , I/O, AUX1, AUX2 = high, CLK not toggling Power down IPCOFF VPC supply current when VCC = 0 CMDVCC is high Min - - - - - Nom 700 - 450 - 345 Max 1500 5 650 5 550 A A Unit A
Rev. 1.3
11
73S8009R Data Sheet
DS_8009R_056
2.6
Voltage / Temperature Fault Detection Circuits
Table 7 lists the voltage / temperature fault detection circuits. Table 7: Voltage / Temperature Fault Detection Circuits Symbol VPCF VCCF Parameter VPC fault (VPC Voltage Supervisor threshold) RDY = 0 (VCC fault, VCC Voltage Supervisor threshold) Die over temperature fault Card over current fault Condition VPC < VCC, a transient event VCC = 5 V VCC = 3 V VCC = 1.8 V TF ICCF - - Min - - - - 115 110 Typical VCC > VPC + 0.3 - - - - - Max - 4.6 2.7 1.65 145 150 C mA Unit V V
12
Rev. 1.3
DS_8009R_056
73S8009R Data Sheet
3 Applications Information
This section provides general usage information for the design and implementation of the 73S8009R.
3.1
Example 73S8009R Schematics
Figure 4 shows a typical application schematic for the implementation of the 73S8009R. Note that minor changes may occur to the reference material from time to time and the reader is encouraged to contact Teridian for the latest information.
CS_from_uC OFF_interrupt_to_uC I/OUC_to/from_uC AUX1UC_to/from_uC AUX2UC_to/from_uC CMDVCC5_from_uC CMDVCC3_from_uC RSTIN_from_uC CLKIN_from_uC RDY_status_to_uC PWRDN_from_uC
See NOTE 3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CS TEST1 N/C OFF I/OUC AUX1UC AUX2UC CMDVCC5 CMDVCC3 RSTIN CLKIN RDY PWRDN TEST2 VDD GND PRES I/O AUX1 AUX2 VCC RST GND CLK N/C N/C PRES VPC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 See NOTE 1 C6 100nF
See NOTE 4 VDD VPC
See NOTE 2 C5 10uF C4 100nF
73S80009R
SO28
VDD R 2 20K ISO7816=1F, EMV=3.3F
Card detection switch is normally closed
C1
8 7 6 5 4 3 2 1
NOTES: 1) VDD = 2.7V to 3.6V DC. 2) VPC = 4.75V to 6.0V DC (Class A-B-C Reader: 1.8V, 3V and 5V cards) 3) Must be tied to GND if not used 4) Internal pull-up allows it to be left open if unused.
10 9
Low ESR (<100mohms) C1 should be placed near the SC connecter contact
SW-2 SW-1
C8 I/O VPP GND C4 CLK RST VCC
CLK track should be routed far from RST, I/O, C4 and C8
Smart Card Connector
Figure 4: Typical 73S8009R Application Schematic
Rev. 1.3
13
73S8009R Data Sheet
DS_8009R_056
3.2
* * *
System Controller Interface
Four separate digital inputs allow direct control of the card interface from the host as follows: Pin CS: Enables the system controller interface. Pin CMDVCC# and/or CMDVCC%: When low, starts an activation sequence. Pin RSTIN: Controls the card Reset signal (when enabled by the sequencer).
Other functions are controlled as follows: * * * * PWRDN places the 73S8009R in a low power mode and shuts down all functions. The card clock is completely controlled by CLKIN. Vcc output voltage valid is indicated on the RDY pin. Interrupt output to the host: As long as the card is not activated, the OFF pin informs the host about the card presence only (low = no card in the reader). When CMDVCC is set low (Card activation sequence requested from the host), a low level on OFF means a fault has been detected (e.g. card removal during card session, or voltage fault, or thermal / over-current fault). This condition automatically initiates a deactivation sequence.
3.3
Power Supply and Voltage Supervision
The Teridian 73S8009R smart card interface IC incorporates a LDO voltage regulator. The voltage output is controlled by the digital input sequence on CMDVCC# and CMDVCC%. This regulator is able to provide either 1.8 V, 3 V or 5 V card voltages from the power supply applied on the VPC pin. Digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage range to interface with the system controller. Three voltage supervisors constantly check the presence of the voltages VDD, VPC and VCC. A card deactivation sequence is forced upon a fault detected by any of these voltage supervisors. The voltage regulator can provide a card current of 65 mA in compliance with EMV 4.1, and of at least 90 mA in compliance with ISO7816-3. The VCC voltage supervisor threshold values are defined from the EMV standard.
3.4
Card Power Supply
The card power supply is internally provided by the LDO regulator. The signals CMDVCC# and CMDVCC% control the turn-on, output voltage value, and turn-off of VCC. When either signal is asserted low, VCC will ramp to the selected value or if both signals are asserted low (within 400 ns of each other), VCC will ramp to 1.8 volts. These signals are edge triggered. If CMDVCC% is asserted low (to command VCC to be 5 V) and at a much later time (greater than 2 s, typically), CMDVCC# is asserted low, it will be ignored (and vice versa). At the assertion (low) of either or both CMDVCC#/CMDVCC% signals, VCC will rise to the requested value. When VCC rises to an acceptable value, and stays above that value for approximately 20 s, RDY will be set high. Approximately 510 s after the fall of CMDVCC#/CMDVCC% the circuit will check the see if VCC is at or above the required minimum value (indicated by RDY=1) and if not, will begin an emergency deactivation sequence. During the 510 s time, over-temperature, card removal, or de-assertion of CMDVCC#/CMDVCC% shall also initiate an emergency deactivation sequence.
14
Rev. 1.3
DS_8009R_056 Choice of the VCC capacitor:
73S8009R Data Sheet
Depending on the application, the requirements in terms of both the VCC minimum voltage and the transient currents that the interface must be able to provide to the card are different. An external capacitor must be connected between the VCC pin and the card ground in order to guarantee stability of the LDO regulator, and to handle the transient requirements. The type and value of this capacitor can be optimized to meet the desired specification. Table 8 shows the recommended capacitors for each VPC power supply configuration and applicable specification. Table 8: Choice of VCC Pin Capacitor Specification Requirements Specification EMV 4.1 ISO-7816-3 & GSM11.11 Min VCC Voltage allowed during transient current 4.6 V 4.5 V Max Transient Current Charge 30 nAs 20 nAs System Requirements Min VPC Power Supply required 4.75 V 4.75 V Capacitor Type X5R/X7R with ESR<100 m Capacitor Value 3.3 F 1 F
3.5
Over-temperature Monitor
A built-in detector monitors die temperature. When an over-temperature condition occurs, a card deactivation sequence is initiated, and an error or fault condition is reported to the system controller via the OFF interrupt.
3.6
Activation and Deactivation Sequence
The host controller is fully responsible for the activation sequencing of the smart card signals CLK, RST, I/O, AUX1 and AUX2. All of these signals are held low when the card is in the deactivated state. Upon card activation (the fall of CMDVCC#/CMDVCC%, all the signals will remain low until RDY goes high. The host should set the signals RSTIN, I/OUC, CLKIN, AUX1UC and AUX2UC low prior to activating the card and allow RDY to go high before transitioning any of these signals. In order to initiate activation, the card must be present and there can be no over-temperature fault and no VDD fault.
At t1 (500 s), if RDY = 0 or overcurrent, circuit will de-activate (safety feature) t1 CMDVCC3 or CMDVCC5 VCC IOUC IO RDY RSTIN RST CLKIN CLK
CLK=CLKIN if RDY=1 Ignored Ignored RST=RSTIN if RDY=1 Ignored IO = IOUC if RDY=1 VCC valid
IO, AUX1, AUX2, CLK, RST are held LOW until RDY = 1 and CMDVCCx = 0
Figure 5: Activation Sequence Rev. 1.3 15
73S8009R Data Sheet
DS_8009R_056
Deactivation is initiated either by the system controller setting CMDVCC#/CMDVCC% high, or automatically in the event of hardware faults. Hardware faults are over-current, over-temperature and card extraction during the session. The host can manage the I/O signals, CLKIN, RSTIN, and CMDVCC#/CMDVCC% to create other de-activation sequences for non-emergency situations.
CMDVCC% or CMDVCC# VCC
~ 100 s
5 - VCC is lowered
I/OUC I/O OFF RSTIN RST CLKIN CLK 3 - CLK forced low approx. 7.5 s after RST falls Note: Host should set STROBE low when OFF goes low, otherwise CLK may be truncated 2 - RST forced low approx. 0.6 s after OFF falls 4 - I/O falls approx 2 s after CLK falls 1 - OFF falls due to card removal or fault
Figure 6: Deactivation Sequence
3.7
* *
OFF and Fault Detection
The system controller can monitor the OFF signal to: Query regarding the card presence outside of a card session Detect faults during card sessions.
Outside a Card Session In this condition, CMDVCC#/CMDVCC%) is always high, OFF is low if the card is not present and high if the card is present. Because it is outside a card session, any fault detection will not act upon the OFF signal. No deactivation is required during this time. During a Card Session In this condition, CMDVCC#/CMDVCC% is always low and OFF falls low if the card is extracted or if any fault is detected. At the same time that OFF is set low, the sequencer automatically starts the deactivation process and the host should stop all transition on the signal lines. Figure 7 shows the timing diagram for the signals CMDVCC#, CMDVCC%, PRES and OFF during a card session and outside the card session.
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73S8009R Data Sheet
OFF is low by card extracted PRES OFF CMDVCC VCC outside card session within card session
OFF is low by any fault
within card session
Figure 7: OFF Activity Outside and Inside a Card Session
3.8
Power-down Operation
A power-down function is provided that disables all analog functions. The power-down state is only allowed in the de-activated condition. The host invokes the power-down state when it is desirable to save power. The signals PRES and PRES are functional in the power-down state so that a card insertion asserts OFF high. If there is no card present (OFF = low) in power-down mode, the pull-up resistor is disabled so that no current is drawn from VDD. If a card is inserted, the pull-up resistor is enabled and OFF goes high. Upon receiving the OFF indication, the host must then de-assert power down (PWRDN) and wait until the circuit is ready. When PWRDN is de-asserted, OFF goes low to indicate that the circuit is not ready (it is going through the power-on recovery time). When the circuit is ready, OFF will go high if the card is present. Figure 8 illustrates the behavior of the circuit for PWRDN events.
PRES
OFF will go high if card is present and there are no faults OFF goes low when PWRDN is de-asserted while circuit starts up
OFF
OFF going high indicates circuit is ready PWRDN while CMDVCCx=0 has no effect PWRDN will have effect when CMDVCCx=1
PWRDN
RC OSC
~30 s
Controller must wait for OFF=1 after setting PWRDN=0 before setting CMDVCC(3/5)=0
~30 s
CMDVCC3 / CMDVCC5
RDY - indicates VCC is OK
Figure 8: Power-down Operation
Rev. 1.3
17
73S8009R Data Sheet
DS_8009R_056
3.9
Chip Select
The CS pin is provided to allow multiple circuits to operate in parallel, driven from the same host control bus. When CS is high, the pins RSTIN, CMDVCC%, CMDVCC# and CLKIN control the chip as described. The pins IOUC, AUX1UC, and AUX2UC operate to transfer data to the smart card via IO, AUX1, and AUX2 when the smart card is activated. IO, AUX1, and AUX2 have 11 K pull-up resistors while OFF and RDY have 20 K pull-up resistors. When CS goes low, the states of the pins RSTIN, CMDVCC%, CMDVCC#, and CLKIN are latched and held internally. The pull-up for pins IOUC, AUX1UC, and AUX2UC become a very weak pull-up of approximately 3 microamperes. No transfer of data is possible between IOUC, AUX1UC, AUX2UC and the smart-card signals IO, AUX1, and AUX2. The signals OFF and RDY are set to high impedance and the internal 20 K pull-up resistors are disconnected. PWRDN is not latched when CS is low. The operation of the fault sensing circuits and card sense inputs (in regards to de-activation) are not affected by CS.
tDZ
CS
tSL
OFF, I/OUC, AUX1UC, AUX2UC
HI-Z STATE
FUNCTIONAL
HI-Z STATE
CONTROL SIGNALS
tIS
tSI
tID
tDI
Figure 9: CS Timing Definitions
3.10 I/O Circuitry and Timing
The states of the I/O, AUX1, and AUX2 pins are low after power-on-reset and they are high when the activation sequencer enables the I/O reception state. See Section 3.6 Activation and Deactivation Sequence for more details on when the I/O reception is enabled. The states of the I/OUC, AUX1UC, and AUX2UC are high after power on reset. Within a card session and when the I/O reception state is turned on, the first I/O line on which a falling edge is detected becomes the input I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected, both I/O lines return to their neutral state. Figure 10 shows the state diagram of how the I/O and I/OUC lines are managed to become input or output. The delay between the I/O signals is shown in Figure 11.
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73S8009R Data Sheet
Neutral State
No
I/O reception
Yes
I/O & not I/OUC
No Yes No I/OUC & not I/O Yes I/OUC in No I/OICC in No
I/OUC
I/O
yes
yes
Figure 10: I/O and I/OUC State Diagram
I/O
I/OUC
tI/O_HL
tI/O_LH
tI/OUC_HL
tI/OUC_LH
tI/O_LH = 15 ns tI/OUC_LH = 15 ns
Delay from I/O to I/OUC: Delay from I/OUC to I/O:
tI/O_HL = 100 ns tI/OUC_HL = 100 ns
Figure 11: I/O to I/OUC Delay Timing Diagram
Rev. 1.3
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73S8009R Data Sheet
DS_8009R_056
4 Mechanical Drawings
4.1 20-pin QFN
4.00 3.75
4.0
20
2.0
2.00 1.875
1 2
1 2
4.0
1.875 2.00 3.75 4.00
3
2.0
TOP VIEW
TOP VIEW
0.18 / 0.30 2.50 / 2.70 1.25 / 1.35
0.85 NOM / 0.90 MAX 0.02 NOM / 0.05 MAX 0.20 REF
0.30
0.20 MIN
2.50 / 2.70
2
K
1.25 / 1.35 1
0.45
SEATING PLANE
20 ID 20
19
0.50
0.20 MIN
SIDE VIEW
BOTTOM VIEW
Figure 12: 20-pin QFN Package Dimensions
20
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73S8009R Data Sheet
4.2
28-Pin SO
.050 TYP. (1.270)
.305 (7.747) .285 (7.239) PIN NO. 1 BEVEL
.715 (18.161) .695 (17.653) .0115 (0.29) .003 (0.076)
.420 (10.668) .390 (9.906)
.110 (2.790) .092 (2.336) .016 nom (0.40)
.335 (8.509) .320 (8.128)
Figure 13: 28-Pin SO Package Dimensions
Rev. 1.3
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73S8009R Data Sheet
DS_8009R_056
5 Ordering Information
Table 9 lists the order numbers and packaging marks used to identify 73S8009R products. Table 9: Order Numbers and Packaging Marks Part Description 73S8009R-SOL, 28-pin Lead-Free SO 73S8009R-SOL, 28-pin Lead-Free SO Tape / Reel 73S8009R-QFN, 20-pin Lead-Free QFN 73S8009R-QFN, 20-pin Lead-Free QFN Tape / Reel Order Number 73S8009R -IL/F 73S8009R -ILR/F 73S8009R -IM/F 73S8009R -IMR/F Packaging Mark 73S8009R -IL 73S8009R -IL 8009R 8009R
6 Related Documentation
The following 73S8009R documents are available from Teridian Semiconductor Corporation: 73S8009R 20QFN Demo Board User Guide 73S8009R 28SO Demo Board User Guide Migrating from the 73S8024RN to the 73S8009R
7 Contact Information
For more information about Teridian Semiconductor products or to check the availability of the 73S8009R, contact us at: 6440 Oak Canyon Road Suite 100 Irvine, CA 92618-5201 Telephone: (714) 508-8800 FAX: (714) 508-8878 Email: scr.support@teridian.com For a complete list of worldwide sales offices, go to http://www.teridian.com.
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DS_8009R_056
73S8009R Data Sheet
Revision History
Revision 1.0 1.2 1.3 Date 8/30/2005 12/11/2007 10/22/2009 Description First publication. Updated 28SO package dimensions. Removed leaded options. Formatted to the new Teridian style. Miscellaneous editorial changes.
Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation. All other trademarks are the property of their respective owners. This Data Sheet is proprietary to Teridian Semiconductor Corporation (TSC) and sets forth design goals for the described product. The data sheet is subject to change. TSC assumes no obligation regarding future manufacture, unless agreed to in writing. If and when manufactured and sold, this product is sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement and limitation of liability. Teridian Semiconductor Corporation (TSC) reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that a data sheet is current before placing orders. TSC assumes no liability for applications assistance. Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com Rev. 1.3 23

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